(a) Field of the Invention
The present invention relates to a semiconductor integrated circuit having a micro processing unit (microprocessor) and a DRAM cache memory on a single chip and, more particularly, to the structure of interconnect lines disposed on the chip.
(b) Description of the Related Art
In view of a low operational speed of a main storage device used for a micro processing unit (MPU) in a computer system, it is usual that the MPU is associated with a cache memory having a higher operational speed. The cache memory temporarily stores some of data for the MPU to compensate the low speed of the main storage device.
In general, the cache memory devices, required to have a higher operational speed, have been implemented by static random access memories (SRAMs), which generally have a larger circuit scale per unit capacity however. Thus, a small-capacity SRAM is generally used heretofore for the cache memory.
It is desirable that a dynamic random access memory (DRAM) having a larger storage capacity per unit area be used as the cache memory for reducing the chip size of the LSI. If the cache memory is to be implemented by a DRAM, a configuration may be employed in that the MPU and bonding pads are disposed in the central area and the peripheral area, respectively, of a semiconductor chip, with the DRAM cache memory disposed between the MPU and the bonding pads.
In the LSI as described above, if the DRAM cache memory and the MPU are separately designed and combined thereafter on a chip, interconnect lines including source lines and signal lines and extending between the bonding pads and the MPU are generally arranged outside the area for the DRAM cache memory. This increases the chip size of the LSI. On the other hand, if the interconnect lines are arranged within the area for the DRAM cache memory, the location for the interconnect lines must conform to the arrangement within the DRAM cache memory. In addition, other interconnect lines extending between the bonding pads and the DRAM cache memory may retard the interconnect lines between the bonding pads and the MPU from extending along routes having minimum lengths.
Moreover, if the noise generated on the overlying interconnect lines, especially on the source line, extending between the bonding pads and the MPU is propagated through the parasitic capacitance to the word lines or the data lines disposed below the overlying interconnect lines, a malfunction may arise in the operation of the DRAM cache memory.
It is therefore an object of the present invention to provide a semiconductor integrated circuit having a MPU and a DRAM cache memory wherein overlying source lines for the DRAM cache memory can be arranged with a suitable density substantially without restriction by the arrangement of the underlying source lines.
It is another object of the present invention to provide a semiconductor integrated circuit which is capable of reducing the noise propagated from the overlying interconnect lines extending between the bonding pads and the MPU to the word lines or data lines formed as the underlying metallic interconnect lines.
It is a further object of the present invention to provide a semiconductor integrated circuit which is capable of reducing the noise propagated from the MPU to the data line of the DRAM cache memory through the source lines.
The present invention provides a semiconductor integrated circuit including a microprocessor disposed substantially in a central area of a chip, a DRAM cache memory including at least one DRAM macro block disposed adjacent to the microprocessor and having a plurality of memory cells arranged in a matrix, bonding pads disposed in a peripheral area of the chip to oppose the microprocessor with the DRAM macro block disposed therebetween, and a plurality of interconnect lines including at least one overlying source line connected between the microprocessor and one of the bonding pads and a plurality of underlying interconnect lines extending below the overlying source line in a direction substantially parallel to a direction of arrangement of the memory cells, the underlying interconnect lines being connected between the overlying source line and the DRAM macro block.
In accordance with the LSI of the present invention, by providing two-layer source lines, the underlying source line providing operating current for the DRAM macro block is less affected by the potential fluctuation of the overlying source line which is caused by the microprocessor having a higher power dissipation.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.